Design spi interface fpga verilog vhdl jobs

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    5,213 design spi interface fpga verilog vhdl jobs found, pricing in USD
    grass cutting robot 6 days left
    VERIFIED

    ...development of ROS based C++/Python code for establishing TeleOp mode. Assist in development of f/e wireframes Right now I have the 4 motors being controlled by arduino using SPI. I am now wanting to send a JSON object from a remote webserver using ROS_bridge to arduino using ROSserial.h. additionally I am interested in transmitting using PCL/lowered

    $16 / hr (Avg Bid)
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    ...use the TI USB Stick that I have dozen on hand and simply add external FRAM. And if we can get FRAM with dual I/O access port - that will give us ability to add external interface (including wireless over Bluetooth) to Computer or mobile device. The one for Display- is working. The second for Sensors you will have to develop the code for. Based on my

    $626 (Avg Bid)
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    ...Modelsim and FPGA. -Programming Language : Verilog HDL. -This project is divided to two parts:- Part 1. Design and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Registe...

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    ...PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Basys3 FPGA development board. The FPGA used is a Xilinx Artix-7 FPGA (XC7A35T-1CPG236C). An asynchronous high-active reset shall be used to initialize the design (BTNC button on the Basys3 board). The whole design uses a 100 MHz clock.

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    verilog counter 5 days left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

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    Here projects are implemented in VHDL programming using Xilinx software. B.E/[login to view URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

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    Data Receiver 4 days left

    I need 4 wireless nodes to connect to each other, ESP8266, each will receive data via SPI which needs to be sent wirelessly and displayed on an Android app, phone/tablet. The hardware is designed just need software.

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    Binford Research Labs is a Robotics and AI based startup based in Hyderabad. We pro...who can work with interfacing various sensors and modules with prominent Microprocessors and Micro-controllers. Work on different protocols and interfaces such as UART, I2C, SPI and MQTT etc. Work with the team to build robust IoT [login to view URL] on Python integration.

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    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [login to view URL] file.

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    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

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    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

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    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit

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    ...Code this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals

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    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

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    Hi, I need a quick prototype of an Artix-7 fpga that makes a pcie to sd card controller (SD host controller/SD bus). Objective is to have a fpga card (working on pcie screamer) recognized as a SD/MMC card reader under windows, I need Windows to recognize/be able to install the windows built-in sd card drivers for the card. I don’t need it to actually

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    ...working on for the past 4 months- an Altera FPGA control system for a specific application. I’ve had the control system previously evaluated by an engineer, although there are aspects of the system I’d like to have double-checked prior to production. I’d like an Electrical Engineer to simply re-confirm my design, and advise on any mistakes I have made

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    Need the C code of the drivers of I2C ,SPI ,TIMER AND PWM in Atmel's microcontroller SAMDA

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    We want a service of Fpga card design and embedded software

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    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

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    You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

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    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    I need a board that has HDMI inpu...video stream. The picture will be fed into the board by some type of data channel (SPI for example). Basically On-Screen display for HDMI. Need PCB to be designed and a prototype built. Important: please let me know how would you approach this problem, would you use FPGA or some type of ASIC, which part number etc.

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    FPGA and CMOS technology questions Just a few hours task Bit at hourly rate

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    Hi, Looking to make a small communication interface on FPGA board, Altera DE2-115. Not to lengthy task, just a 4 signal interface. Use Quartus. Communication interface name, XY2-100 Max time, 3 days.

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    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. HI there, wondering if you ha...profile and would like to offer you my project. We can discuss any details over chat. HI there, wondering if you have the ability to create a bitstream for the XILINX VCU 1525 FPGA to mine cryptocurrency.

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    Write python code for write instruction. I will give the details of instruction

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    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

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    Hello.. interested in a bitstream / miner for vu9p fpga card - VCU1525 -- let me know how much and if you can target equihash 150,5

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    Hi I am looking to offload a embedded system project which requires deep understanding of a) Hardware board design b) FPGA/RTL Developer c) Linux device driver expert d) software expert e) Signal processing expert

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    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture WE PREFER: - Experience with HW synthesis tools for ASIC/FPGA - Knowledge of versioning tools (Git, SVN) - Ability

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    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

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    Write python code for spi transfer raspberry using write commend

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    Serial Communication between Arduino Mega boards using Serial, I2C and SPI communication.

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    ...RGB interface. In addition, the image will require interpolation while keeping the original aspect ratio. Source device will be provided + timing chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    ...different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements, specs of FPGA, plan and ...

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    Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL

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    I need you to develop Grin coin bitstream and provide miner compatible with BCU1525 FPGA.

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    I have a VHDL code. Then It has some issue. I need to fix it within a few hours. If you are electronic expert you can do it within 1 hours. I'll send details via interviewing. Ivan.

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    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    I got DE2 115 FPGA board and to implement the LOW pass filter using MATLAB simulink.

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    ...kind of language (eg. C/C++) to run on a Raspberry Pi or similar device. Multithreading will be necessary to ensure reliable performance. The application monitors a sensor over SPI and given the right conditions records a period of time (including a buffer). It also has a number of other peripherals like RTC, GPS, GSM, a few LEDs and communicates over Ethernet

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    About the position: As the firmware/embedded software engineer, you will be responsible for design, development and testing of embedded software and firmware using HT5019 SOC. Job Description: .Develop firmware for microcontroller-based custom hardware (32 bit) .Evaluate, test, and review designs to determine if program will perform according to

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    I need you to develop bitstream algo (FPGA) for me. I would like this as soon as possible.

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    We need to make the software with a PIC...phase power and energy meter with the IC : ADE7758. The AD7758 should measure the power, energy, voltage, current and temperature variables and send to PIC micro controller via SPI, after this , the PIC micro controller should send the information with a proprietary protocol trough ESP8266 to internet fix IP.

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