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    3,264 pic32 fpga jobs found, pricing in USD

    We have a zedboard code which takes data from external adc and transfer over ethernet to pc. Everything is working fine. After data acquisition, we are transferring data of around 75k samples of 16 bit each to PC. Its taking around 3 min for transfer. Need work on data transfer rate and improve the same.

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    FPGA xilinks 3 days left
    VERIFIED

    Needed specialist for modify and compile cores for xilinks FPGA ,

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    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

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    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

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    Need to convert MATLAB code to synthesizable VHDL code. I am using DE2 FPGA board for testing

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    I need a bitstream and a Linux-adapted mining software for my JungleCat with VU35P from Xillien. Freelancer will provide Bitstream and I will test its hash rate and stability. A board can also be provided for testing. Also, I need long-term support. Also write the word VCU at the end of the offer.

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    Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.

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    I will love to chat with you about my project. Please let me know when you can https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details

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    I will love to chat with you about my project. Please let me know when you can https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details

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    I have a project i want to talk to you about https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details Please let me know when you have time to chat

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    We are looking for someone that has deep experience in programming FPGA for RF instances. We have a need to send and receive over 30mbps and hoping to find someone with some experience in this and can guide us through a PRACTICAL code or system they built or better yet give us some learning tutorials with what they have built.

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    We are looking an expert over crosslink-NX to support design for a camera aggregator. We would like to hear from you, skills and experience with other projects.

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    We are looking for an expert over crosslink-NX to support the design of a camera aggregator. We would like to hear from you, about your skills and experience with other projects. please describe your recent experience with similar projects

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    Need to make a simulation and implement a novel more advanced multiplier circuit. It would be preferable if FPGA is used. It should then be documented properly

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    Hi Harish Kumar,I noticed your profile and would like to offer you my project. The requirement for my project is to build a Cryptoprocessor using RISC -V Architecture on Vivaldo. We would be running a lightweight Cipher used in EV control unit (EV-ECU) . Aim is to carry out additional customization of instructi...(EV-ECU) . Aim is to carry out additional customization of instruction of Chiper, inject errors and collect data. Thereafter analyse the data obtained using AI-ML and be able to predict the type of error. The first stage is to Create the Cryptoprocessor on Vivaldo. I have found a research topic that guides on the same. . Need your guidance and help in this regard. We can discuss any details over chat.

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    Hi ePlatinum, I noticed your profile and would like to offer you my project. The requirement for my project is to build a Cryptoprocessor using RISC -V Architecture on Vivaldo. We would be running a lightweight Cipher used in EV control unit (EV-ECU) . Aim is to carry out additional customization of instructio...(EV-ECU) . Aim is to carry out additional customization of instruction of Chiper, inject errors and collect data. Thereafter analyse the data obtained using AI-ML and be able to predict the type of error. The first stage is to Create the Cryptoprocessor on Vivaldo. I have found a research topic that guides on the same. . Need your guidance and help in this regard. We can discuss any details over chat.

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    - write Verilog code for steganography algorithm so that I can be implemented on FPGA - using Verilog Xilinx ise have to write module code & test bench where it can be implemented on Fpga

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    Consulting videocall in hardware architecture and FPGA/RTL to solve general doubts and help enlisting contents for future training.

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    I am looking for an FPGA (Verilog) expert who can help me to troubleshoot and implement the EdDSA algorithm in Xilinx Vivado Design Suite. The Vivado project file is available in the attachments and several modules of the project are already completed. Looking for an expert who can do it in 3 to 4 days. Further information will be provided in the discussion.

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    I would like to learn more about Hardware to prepare myself to work with the development of device drivers for more complex hardware. I need someone with knowledge and/or work experience of either projecting hardware -- especially within the PCI/PCIe realm -- or developing device drivers for this kind of hardware. 1) The hardware basics: Interrupts, DMA, DRAM/SRAM(&caching), multicore & multithreading, etc - under the hoods (I know what they are, I need to understand how they work and how they interact with each other - i.e. how cpu is selected to process an interrupt). Schematics - basic notions for reading schematics, hardware documentation, etc. 2) RTL: key concepts and definitions. How and what to study about them. Where to find information. Brief introduction. 3) FPGAs: key ...

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    Using Pynq Z2 FPGA to connect a camera (OV7670 - CMOS Sensor), and then display the video on a monitor through HDMI output. The Project is built using VHDL language and IP blocks. The purpose of this it's to build also nurual network to recognize a face/person so the camera can follow the object using servo motor.

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    Verilog FPGA Code implementation of FEC RS(198, 194) decoder.

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    ...have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · Tools &nd...

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    The project consists in implementing a buffer delay on a 100G traffic done in an Xilinx Alveo FPGA

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    I need to design a Hilbert transform and test it in Matlab before implementing it on FPGA. I have never created a Hilbert transform with Matlab without the hilbert() function, and the function does not return coefficients. I can't find the documentation on how to do it. I need someone to help with it. The Matlab code must also use the filter on sample data and return complex values after the transform. You should provide the Matlab code used to create the filter and get the coefficients. I will pay $70 USD for the task.

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    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Hello, I need a Lattice FPGA specialist to review my simple LCMX02 Lattice PLD design. I can not make it work, and some help is needed to understand why the PLD does not respond to the JTAG file. This is a very specific project, specifically for Lattice FPGA. I designed with other types of FPGA, and got stuck when I switched to Lattice family of parts. Thank you!

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    code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Creating 2-chain Arbiter PUF on specific FPGA with 64-stages MUX for each chain. The output response PUF will be sent to external device, i.e. Arduino (microcontroller). On the other words, the output response PUF will be processed further on Arduino/microcontroller device

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    It is required to generate arbitrary signals in FPGA for Real Time Controls using Servo Proportional Valve with Control signals of ( +/- 10 VDC ). The various types of other signal generation in FPGA besides Arbitrary signal can be Square, Sine, Triangular. Generation of white noise signal for Real time control is also required.

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    Need help with code and set up for SPI protocol to send data from an FPGA to a GPU, explain code/software procedure and wiring. can forward technical specs for both devices to be used

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project.

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    A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.

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    Hi. Attached a few spike from scope capture. Need at least 8 channels simultaniously. 1. how to get detect these with a precision of 1mV? 2. how to get the value in stm32? (worked with these a lot) (or do we need an fpga) Freq is 200hz at first. Looking to get to 1 khz in the near future. Duration of the spike is only 5 to 12 microseconds. What is the best way to do this precisely ? heard tons of ideas (peak-detect circuit, 20 msps adc, etc ) , but need real proven experience. !!! please apply only if done this succefully. In the opening bid propose direclty your solution. Biggest bids will be disqualified. Stop bidding the top of freelancers brackets. No B*****S approach. Will be paid only if it WORKS! Need STM32 code, parts id, and pcb design.

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    LabView- Code for FPGA to read temperatures from MLX90614 Sensor using I2C Protocol and Compact-RIO Hardware.

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    The project requires an Embedded Programmer having experience in Driver Programming for FPGA cards, PCIe Interface and YOCTO as well as upbringing the Linux OS. Please DO NOT APPLY, if you DO NOT HAVE THE REQUIRED EXPERIENCE.

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    I need a survey paper based on 3 articles at your choose from with publication date more recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, ...recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, VLIW, etc.) B. Micro-architectures optimized for digital signal processing (e.g., multi-port memory, SIMD register banks, multi-core, multi-threading, etc.) C. Accelerators for digital signal processing (rapid deployments / energy efficient with FPGA, GPU, etc.) The paper must be written in latex format. 4 pages, 3-4 figures (explained) and also some references from other articles.

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    Implement the circuit design in the FPGA, and read input /write output to the file. Including timing analysis, power consumption and pin planner etc... Using Quartus prime

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    I need to do simple FPGA project on Boolean Board (Real Digital). For example Tic Tac Toe game. software should be Vivado and programming should be done in Verilog.

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    Program on vivado (verilog), morse code. Binary for "BASYS 3" fpga, simulation, files...etc More details via chat

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    ...sent) and get quotes from them. I will provide an email you can use to email each vendor. I have also provided a link to the item. They can’t be any random emails. I need screenshots of the company’s website and the contact information for each company. Item: FPGA STRATIX 10 2912FBGA (1SX250HH2F55E2VG) Part Link: Hello, my name is Edwin Mendez. I am writing this email on behalf of my company. We are looking for a particular part. The part that we are searching for is the FPGA STRATIX 10 2912FBGA (1SX250HH2F55E2VG). We need three of these parts ASAP. It would be great if you can provide us with this particular part. We are ready for any deal regarding the price structure. We can also schedule a meeting for any further discussions.

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    ...the LoRa based on existing PCB design. RBtec ALREADY has a working board with the main CPU based on PIC32. You do not need to do ANYTHING with the PIC32 other than to communicate with it over UART. This is the product page. The expectation is to design firmware for the STM32 + E22-900M22S LoRa chips. The STM32 communicates with our PIC32 Central CPU over Modbus UART. The communication logic is: RBtec sensor cable <-> PIC32 <- Com modbus UART -> STM32 <-> LoRa <- RBtec protocol-> Gateway The purpose of the project is: I have multiple processors boards (PIC32) in the field with end unit nodes that send UART communication and dry contact relay form and I want to

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    I have rich experience with FPGA I developed FPGA based IDS(Intrusion Detection System) I am strong at C, C++, Verilog and son on

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

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    We hire freelancers who have 1 to 3 hours of free time per day and need a better iPhone 7 or above that can perform and complete testing tasks well. Test system design. Areas of expertise include embedded system/FPGA development, hardware prototype stability and testing. We make the world a better place through innovation and collaboration. From the bottom of the ocean to outer space, you can contribute to the important work of a company whose values are made up of diversity, fairness and inclusion. We are committed to creating a warm, respectful and inclusive environment for all of our teammates and providing them with good career development opportunities. Find the future with us.

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    THE FULL PROJECT DESCRIPTION IS ATTACHED!! This is a FIRMWARE project NOT a PCB design. Development and design of a working LoRa Radio system with basic configuration software for the LoRa based on existing PCB design. The expectation is to design a firmware based on STM32 + E22-900M22S chips. The STM32 communicates with our PIC32 Central CPU over Modbus UART. The communication logic is: RBtec sensor <-> PIC32 <- Com modbus UART -> STM32 <-> LoRa <- RBtec protocol-> Gateway The purpose of the project is: I have multiple processors in the field with end unit nodes that send UART communication and dry contact relay form and I want to connect all nodes through LoRa Mesh to a central hub/gateway that will activate relay alarms centrally for all devic...

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    I am looking for embedded developer to help me on preparing linux image for FPGA and SOC chip . Have samples and you need to follow and prepare the image

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