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    10,057 verilog vhdl perl jobs found, pricing in USD

    ...-Programming Language : Verilog HDL. -This project is divided to two parts:- Part 1. Design and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x

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    General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Ba...

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    verilog counter 5 days left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

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    Here projects are implemented in VHDL programming using Xilinx software. B.E/[login to view URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

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    fix perl code 4 days left

    fix perl code project .Good skills in perl required

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    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [login to view URL] file.

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit

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    ...this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals and

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

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    You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

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    We need a very simple script in perl which can identify bracket balancing for a string of line. It can display the index where the bracket is not balanced or any syntax error.

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    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    I have 2 data files, one is a CSV with a unique ID. The other is a master dat...master data file that is pipe delimited. I need to match 2 fields in each of the data files, and pull the record from the pipe delimited file. Please quote to setup create a perl script that will do everything quoted above. Any questions, please don't hesitate to ask.

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    I'm looking for a PERL expert which is able to modify the script "xFileSharing", in order to provide a way to add the downloader's IP address into the generated file's metadata and/or into any other read-only data and guide us into doing it on our side. xFileSharing has to be already owned by the freelancer who is willing to complete this task, as

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    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

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    Perl scripting Perl scripting Perl scripting

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    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

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    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

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    Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL

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    I have a VHDL code. Then It has some issue. I need to fix it within a few hours. If you are electronic expert you can do it within 1 hours. I'll send details via interviewing. Ivan.

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    Hi there, I need a simple script (php/python or perl) that will make a POST request with an email address from an input file. Based on the response , I need to save/discard the email address. If you need more info, contact me please.

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    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    ...KSH scripts and PERL. The resource should be able to navigate the syntax and semantics of the code comfortably to capture the purpose it as a functional document along with a Business Analyst (BA). The required proficiency of KSH / PERL would be at least that of 6-8 years experienced who is expected capable not only on KSH and PERL but understand the

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    perl expert required to fix scripts. Skills required : Perl, SNMP Monitoring tools

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    I need integrate amazon pay in my websites. my website is in perl language

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    i need to integrate amazon pay to my website perl script expert needed

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    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

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    need a automation expert in python shell and perl

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    Bug-fix Mining App and FPGA-VHDL Project. You have to fix the mining App what is written in C and running on a Linux server. And fix on the FPGA side the PLL and add multicores.

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    need to migrate the Sybase connection,library and SQL to PostgreSQL using perl script

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    I would like to implement a calculator which takes inputs from the ps2 keyboard and displays them on 7 segment.

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    Looking for R language or perl language experts it will take hardly 15min

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    We have an extensive amount of Perl code running a portion of our online platform (we refer to this portion as the Engine) -- and we need to find a Perl expert who can quickly learn our existing Perl code base and then make several improvements. This particular project is for the first two improvements only (numbered list below), but we have a significant

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    NDA
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    longpoll Perl script to register user name , country , province , city , client id , phone number , subscription and program enrolled on telegram bot. if user re-register to the bot, script should take it as profile update. script will delete the user info if user want to unsubscribe from the list. script will trigger with bot start and give option

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    1. Script will be long polling every one hour during 24 hours and change this duration to 15 mins between the hours set by time variable t1 and t2. Eg : t1=0500 t2= 0730. Or t1= 1330 t2=1600 . 2. In a folder location set by variable “folderpath” , When script finds a file set by variable “completionfile” , parse this file and assign values to elements of array...

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    Tutor/Mentor Required(Online): -- Good knowledge of Embedded c/c++ and VHDL -- Good Experience with Renesas Microcontrollers and e2 Studio

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    Muktiplexer of 2 to 1 in vhdl using tje software xillinix

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    more details will be given in the chat only serious expert and my maximum budget for this task is $100

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