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    9,843 verilog vhdl perl jobs found, pricing in USD

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

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    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $146 (Avg Bid)
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    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

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    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamÄ™ on LCD [login to view URL]

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    Help required parsing HTML in Perl, I'm currently using Mojo::DOM but am having problems finding out how to update inline styles. No rendering is required, this is parsing exercise only. Typical tasks are as follows; 1) Find All [id^="conTaID"] Update style width:100% and max-width:600px; 2) Find All [id^="conTaID"] Remove one class 3) Find All [id^="conTaID&q...

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    DSP48E1 help 2 days left

    Hi! I need some help with DSP48E1 verilog instantiation.

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    I have source code for webapplication written in perl on a linux platform from a vendor with out any documentation . I need help with setting up the code to be able to compile for updates

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    i have two perl functions need to convert them in to php or different language

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    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

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    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

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    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

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    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

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    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

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    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

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    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

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    I need you to inspect a website and some problems ! I want to find out what they detect as a returning user

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    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

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    I need help with the structural in Xilinx. I will give you full details. Regards

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    ...am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

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    Hi, my name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the

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    verilog coding using putty or terminal. if you are interested i will give more information.

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    I want help with system Verilog coding. I have a working code that I want revised a bit.

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    Implement an AD2949 IC input block and some more

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    Develop python script. The script should login to AWS docker instances and execute the below command . The drawback of below is that it can be run at container level not at the service level. Since each of docker container runs difference services how can we make sure we can add latency specific to service instead of the entire container box. sudo tc qdisc add dev eth0 root netem latency 1000ms...

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    mtech Verilog project

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    looking for someone who can convert Open CL algorithm into FPGA Verilog project

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    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

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    , the dircetory and file name are using international character and have multiple words

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    From the file uploaded. Need Perl scripts to count frequency of desired occurrences and extract information in a separate text file. More details will be later

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    Hi there, There is an exiting perl script, that makes a Java job run on my Ubuntu machine. However, somehow I don't manage to make it run (on a daily basis) via cronjob. So the 'only' thing you need to do: make the cronjob run. Thanks!

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    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

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    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

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    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

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    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

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    we have a GET function which pulls all records. Now we need new endpoint for filtering those records based on date, type etc DB is Mongo

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    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

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    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

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    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

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    1. Script will be long polling every one hour during 24 hours and change this duration to 15 mins between the hours set by time variable t1 and t2. Eg : t1=0500 t2= 0730. Or t1= 1330 t2=1600 . 2. In a folder location set by variable “folderpath” , When script finds a file set by variable “completionfile” , parse this file and assign values to elements of array...

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    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

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    Need to write a simple script to unlock the user on Oracle and Sql Server databases using perl script..

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    Need to write a script to unlock the user on Oracle and Sql Server databases using perl script..

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    I am looking for the scripts that can induce latency between two micro services deployed on AWS.

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    Revise Practice Tests... Provide Counsultation

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    I have installed ActivePerl on centos and from command line work . When i start same command from task cron job of plesk i have this error Can't locate XML/[login to view URL] in @INC (you may need to install the XML::Twig module) (@INC contains: /opt/ActivePerl-5.26/site/lib /opt/ActivePerl-5.26/lib) at [login to view URL] line 8. BEGIN failed--compilation aborted at [login to view URL] lin...

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    Hey, I am looking for Perl Developer who can work on a simple CGI script on forms. I will give you more details

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    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be ...individual modules are successfully executing but the final result doesn't appear which you can help me in debugging the same ) Note: Problem in debugging the code Language used : VHDL

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    Ok, let try, I am new to these tech issues. I created a blog with blogger, actuall...paypal for subscriptions, but paypal has a function where they will generate usernames and passwords for clients subscribing to my subscription but I would need to install a perl script, well anyways I have attached a file where you can actually read the instructions.

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    if you have rich experience in perl and CGI ,please contact to me and i will give you some detail about my task.

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