W5300 verilog vhdl jobs

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    3,051 w5300 verilog vhdl jobs found, pricing in USD

    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

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    I have a task on verilog and i want someone who is experience on it to help me with it. Please bid only if you know youre an expert. I will share details with interested freelancer. Budget is limited, hiring will be on a weekly basis

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    Hi, I need a basic example of a state machine in VERILOG. We need to find the pattern "100" using machine states. We have 4 states: S0: Initial state S1: If 1 is found S2: If 0 is found S3: If 0 is found Encoding: S0: 00 S1: 01 S2: 11 S3: 10 Transition: Actual state / Input / Next state 00 - 0 - 00 00 - 1 - 01 01 - 0 - 11 01 - 1 - 01 11 - 0 - 10 11 - 1 - 01 10 - 0 - 00 10 - 1 - 01 T...

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    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

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    FPGA and Vhdl expert needed 1 day left
    VERIFIED

    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

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    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Needs to hire 3 Freelancers We are a small and growing company offering consulting and engineering services in many different areas of industry. Here you can find more about us: [login to view URL] In order to enforce our team, we are seeking embedded systems designers with experience in the following domains: * PCB design (Altium Designer, Eagle, KiCAD, PCAD...) * Firmware design (C/C++, assembl...

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    Hi, We are looking for an experienced electronics engineer and software engineer, The project is to design a smart Home Cinema controller, the aim is to send data to a database, reading and writing data of different Video Projectors, Amplifiers, and many more devices via HDMI, USB, RS232, Ethernet, IR and many more. You will conceptualise the electronics and software for the system. We are stric...

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    Hi, I need : * ANN IN FPGA using my mac unit? *zybo-zynq-7000-arm-fpga-soc-trainer-board/ *verilog *MNIST

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    Create a design with two counters and a 7-Segment Display • The first “Fast Counter” should count up 0 -> 49999999 and then reset to zero • When the Fast Counter reaches 49999999 it should output a single pulse on the “o_max_val” output to the second counter • The second counter (4-bit) counter should include a “i_count_enable” input, connected...

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    fix bug in verilog hdl for 8 bit

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    Design an 8-bit microprocessor using Verilog HDL by using Structural Verilog modelling. The individual components can be designed using behavioral modelling. Mandatory components: Instruction Memory Register File Data Memory ALU Control Unit Multiplexers Sign extend unit Program counter The Register File has two registers R0 and R1. Design the program counter and instruction memory such that input...

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    Enable all the listed hardware as the attached image. (2xMarvell ETH, MIG-DDR3, SD, QSPI Flash, PS-DDR3, uart) 2. Install Configured Petalinux, with Python, Flask, numpy, Pillow, littleCMS . Boot with QSPI (We will access this board on the Ethernet, make ETH0 DCHP and ETH1 Fixed @ [login to view URL]) 3. Display JPEG/TIFF image file from SD in webpage. 4. Add one function Button, send the...

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    I have the algorithm of what I want to implement, I just need help a second eye to help me understand how to implement it.

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    Implementation of Fractional order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please.

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    I need a simple VHDL program for measuring the time between two input signals. The VHDL program should be in structural code and should includes modules like Counter, BCDtoASCI, UART and FStateMachine + top level. I need also for every module and for the hole program testbenches.

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    VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation. Verilog files and simple testbench to prove the design. ASIC

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    Hey, I have working project in simulation that when I try to run it on board it doesn't work. I need someone with that board or that have familiar board to notice if there is problem with my code.

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    This includes the development of vhdl code for PWM generator, PID controller, flux estimator etc. Training would be web based on Skype or webex.

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    I am looking for someone who can design a FPGA based hash algorithm including blake bmw sha512 skein luffa shavite simd echo hamsi shabal whirlpool and jh. Developer need to complete FPGA bitstream, and provide verilog source codes.

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    I want to implement a paper using verilog coding.. Kindly review paper before biding

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    It is required to design a 4-bit binary divider. The division can be limited to un-signed numbers only. Feel free to implement the divider by any architecture you like, but be sure to understand and be able to verify the operation of the selected architecture. Fig. 1 shows a binary division example to recap the binary division process. -Structural and behavioral codes for the binary divider using...

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    I Have mips in VHDL code, I want to add to it UART

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    I got MIPS in VHDL, but when I run it on FPGA, It seems to do nothing, although it's working in simulation.

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    Pipelined dual thread core processor design using system verilog, quartus software and altera development board. Please read pdf for detailed information.

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    Anyone who has hands on in verilog on An Accelerator-Based Video Display can help me

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    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [login to view URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 through [logi...

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    Anyone who is good in verilog and worked on Accelerator-Based Video Display can ping me

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    Anyone who has experience or worked on An Accelerator-Based Video Display using verilog can consult me.

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    Display image on the monitor using cyclone V fpga (tool quartus prime Lite edition) , i2c controller using qsys must be used to connect to hardware using verilog.

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    1. Required verilog code for matrix multiplication(systolic architecture) 2. It should Work for large matrix multiplication (Ex: A=170x512 & B=512x125. C=A.B) 3. Also Work for matrix and vector multiplication 4. code should synthesizable and 5. Xilinx FPGA(Zedboard) implementation required 6. Need full block diagram and explanation for systolic matrix multiplication

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    Design a multifunction wristwatch that has time-keeping, alarm, and stopwatch functions. The wristwatch has three buttons (B1, B2, and B3) that are used to change the mode, set the time, set the alarm, start and stop the stopwatch, and so on. Pushing button B1 changes the mode from Time to Alarm to Stopwatch and back to Time. The functions of other buttons vary depending on the mode.

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    RTL design project All of the data required to explain what I want are found in the attached file

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    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [login to view URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 through [logi...

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    Anyone who is good in VHDL and can help me in implementing load, move, add, xor

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    Design a circuit that emulates an alarm system, which is armed and disarmed with a code consisting of 4 symbols given by the buttons on the board (for example btnC, btnL, btnR, btnU). The alarm is armed or disarmed when the correct code combination is entered. When the alarm is disarmed, LED0 is on, when the alarm is armed, LED15 is on. SW0 is a sensor, when the alarm is armed and SW0 = 1, the LED...

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    I need a vhdl project that integrates IoT and communications.

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    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [login to view URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 through [logi...

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    Technology research is already done. Internal FPGA system architecture is already designed. Therefore we only need you to implement and document it. Project is already split and documented as 10 milestones so that development can be done incrementally, step by step, and reviewed/monitored. Project is mostly Verilog development. Some simple programming necessary as well. Documentation is required...

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    I need single cycle 32 bit mips vhdl coding to find prime numbers. I will provide code to find prime number so you just have to build cpu for this specific purpose and I am also going to provide parameters for this architecture. I am gonna share project file after finalising with best person to do this job

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    We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado. There are 5 blocks in total with the following functionalities: 1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 2. RDM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and test...

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    I'm a electronic engineer and I have a good command on computer programs and also on digital programming like VHDL.

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    You have to write code and report for this .

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    In this project, you are required to develop a structural Floating-Point Unit (FPU) for use with a microprocessor. The processor needs to be capable of floating point addition and multiplication. The numbers are to be encoded into IEEE 754 single precision 32-bit format. The FPU should also be able to detect and flag the 'NaN' cases. For the project demonstration, interface the FPU to...

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    I have the scheme of the project need only to work with the basys 3. Only to use buttons and switches from the basys3. Need the whole code in VHDL for Vivado.

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    Develop a 32‐bit single or multi‐cycle CPU capable of performing a search for prime numbers.    CPU

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    We are looking for an experienced FPGA developer to write technical documentation related to Xilinx and Verilog development as well as custom hardware accelerators. Content is in the form of educational papers for semi-technical audience. Each article/paper is expected to be around 1900 words (4-5 pages, plus custom diagrams/infographics). Candidates must be able to prove experience in RTL/Verilo...

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    Has to be completed by the end of tomorrow (13/05/2019) Create VHDL code for chess clock, uploaded the task as a file.

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