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    133 jobs found, pricing in USD

    in the project there is a basic game. There are some walls placed vertically and an object slides and try to avoid crash these walls by using up and down buttons on FPGA. it is not mandatory to be a complex project. I need to have in a week.

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    Radar Engineer is needed 5 days left
    VERIFIED

    I need a radar engineer with an academic writing skills.

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    Hi, I want a 2D convolution module in Verilog, using DSPs.

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    DSP48 Macro teacher needed 4 days left
    VERIFIED

    Hello, I want to learn how to use LogiCORE DSP48 Macro. I need someone who can teach me everything about this IP core and guide me on how to do simple circuits.

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    1. Can You make your own version of hardware decoder based on the decoding algorithm. the number of bits however should be remain the same is 64×64,(the decoding methods SISO decoding and Chase Pandiah, type 2 Chase algorithm) and after simulate the decoder on Xilinx ISE and coding in VHDL. 2. and write a brief report explanation how is the hardware structure work and etc.

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    I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

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    BId only if u can do only the second Part for $50 and within 3 days stereoscopic vision system the aim stereo vision uses two adjacent cameras to creat a 3d image of the world . A depth map can be created by comparing the offset of the corresponding pixels from the two [login to view URL] for real time stereo vision the image data needs to be processed at a reasonabale frame rate .real-time stereo vision allows for mobile robots to more easily navigate and interact with objects by providing both the images from the cameras and depth of the [login to view URL] the image processing can be parallelized in order to increase the processing speed .fpga are highly parallelizable and lend themselves well to this problem Requirements. 1, Implement the software system on opengl by drawing a cube by dropping it and seeing it through a stereoscope lensIn perspective projection and the use of two center projection (off-axis projection) 2,Implement hardware system using vhdl language and xilinx 9.2i software And executed on spartan -3e linen The graphic is displayed on an external screen only the second Part

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    in this project i need just read a analog signal on altera cyclone 5 board and also to realize pt1 element with simple response a(t)=(1-e^-t/T)....it's a simple project and i can explain you in more detail ....so i just want this to signal at the out i.e on gpio pins

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    I am looking for a FPGA programming expert to work on my project. More details will be shared with only those who share references of past work in FPGA.

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    Project for Haroon A. 16h left
    VERIFIED

    Hi Haroon A., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    I have a serial adder that I need converted to serial multiplier in system Verilog. very easy only 1 hour work

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    I require source code for the design and simulation verification of a calculator (Not + - / * operations) with slightly more experienced VHDL'ers can be selected for this quick project

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    I require a VHDL deisgn code, to construct a simple calculator for two input numbers, testbench and simulation for verification of functionality before using the board.

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    I am looking for a FPGA programming expert to work on a project. More details will be shared with only those who share references of past work in FPGA

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    FPGA programming 3 days left
    VERIFIED

    We are looking for one freelancer to develop FPGA software for Cryptonight mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be perfectly optimized. You will work in our office in our country in Europe or you can work remotely if you have necessary equipment. We'll provide food and accommodation. You will be hired with a regular working contract with NDA. Deadline to complete the programming is 30 to 60 days. So you MUST be expert at programming FPGAs. You will get paid at the END of the job once successfully accomplished. We are asking for a FPGA programming references from the applicants. For further details please contact me.

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    - PCI transmition logic implement with ZC102 board and Xilinx PCI Solution v1.3 - windows device - sample wndows program

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    I have a Spartan 6 lx9 dev board. I would to connect the board to my computer and perform standard arithmetic calculations and will require help setting up the calculator.

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    Build a radio communication system which can transmit and receive voice signals over ISM band. Design the system with LabView and USRP NI 2901. You can choose the parameters such as modulation techniques as you like.

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    I want someone to make a 40 minutes video to teach me how to Use cadence tool to synthesize digital circuit from Verilog code and simulation and do the static timing analysis and static power analysis in a given digital circuit which contains XORs and Multiplexers

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    A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.

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    Looking for someone to help me with computer architecture. You need to be advanced using VHDL. Make a proposal and I'll go into more details.

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    I am having difficulties in finishing my final year project. I would like to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not quite sure with the Verilog language itself and how to do the coding for fft. And there's a little problem with the software where I'm not able to simulate even with the simplest design (I tried with full adder). I found a butterfly unit code in some website which might be related with my project. But, I don't know how to do the test bench code part. Attached is the code. If someone could help with this project, I would like to have it on 2nd May 2018. Thank you.

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    Serializer & Desrializer Implementation using ZC706 and MTX

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    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using four wires servo(PWM Vcc GND feedback). But I cannot find this kind of servo in the online shops. Actually, I have some plans. a. writing an algorithm like this blog, [login to view URL] b. using some sensors like Accelerometer Magnetometer Gyroscope. But I think there might be several problems. For accelerometer and gyroscope. Integral will increase error during continuous operation? For magnetometer. Electromagnetic effect induced by servos and CMOS camera might cause bad data? Or, any other sensors I haven't mentioned will work better? Therefore, I think we need some chat to find a solution before start working. FPGA: Xilinx Basys3 Language: Verilog HDL Software: Vivado 2015.4

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    Hi there Please check the document

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    Hi there Please check the document!

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    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

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    I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time required to do the job.

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    Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

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    I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [login to view URL] Please respond directly with any questions such as specific mining software and such.

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    expert in vivado and vhdl needed asap

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    using four bit ALU, given two numbers A and B we need to find if A is divisible by B

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    Program a FPGA to work as a MC6803 on a device like a Digilent Cmod A7: Breadboardable Artix-7 FPGA Module. [login to view URL] . will need relevant information to program multiple devices.

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    I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture.

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    I am looking for someone who is familiar with and have access to the following Electronic systems/subjects: - Op-Amps - Multisim - FPGA/Quartus PRime - Mbed Microcontrollers - Digital Analogue converters (DAC) - using R-2R Ladder If you do not have relevant skills and access please do not apply Thank you

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    I have a project where i need to receive ads54j20 data with interface jesd204b on vc707. if your are interested please let me know and we can discuss details in a chat.

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    Is it possible to make an custom made Arduino Pro Mini PCB? It needed to be made trough easyeda pcb and components from 1206 package Remove all holes traces that are x out. Remove reset button ? It needed to be programmable by and FTDI1232 programmer as regular arduino pro It also needed to added some other components to the board.I have a template that needed to be edited on easyeda, that you will get access to. Template added...but it is not working... Let me know if this is something you can change :)

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    I have some work in MATLAB i need this work to be finished asap (1-2 days lower bids would be preferred i have more work like this so i want serious freelancers Time wasters are not allowed to bid here NOTE: Milestone will be after seeing the full work

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    Embedded Systems Ended
    VERIFIED

    use quartus compiler/simulator to design a [login to view URL] displays left 16 bits of the result in hexadecimal format......................................................

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    I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details

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    I am looking for a person who will make FPGA NIST5 Cryptocurrency miner. I need full unrolled NIST5 core. NIST5: blake512 -> groest512 -> jh512 -> keccak512 -> skein512 Perfect performance: 1x (Example: FPGA at 400MHz clock generates 400Mega Hash / secound) Language: VHDL FPGA: Xilinx 7 series

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    Hi This is my research project. i want to design a video codec h.264 processor for face recognition. i this project i wrote verilog hdl coding and completed Ai algorithm for face recognition. so the next steps is to do the cross compilation of h.264 verilog coding with AI Algorithm. so iam expecting that to complete cross compilisation of h.264 verilog code with Ai algorithm. regards

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    this is my problem : " 'XPAR_AXI_GPIO_0_BASEADDR' undeclared (first use in this function)"

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    A stepper motor controller in verilog ,

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    projekt może być oparty na chipie ADV7181

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    vhdl expert needed2 Ended
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    Expert in VHDL is needed to do a project

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    Design and develop a interface logic for reading and writing to and from eMMC device to support 300Mbps data rate to Video encoder. - timelines - 2-3 weeks.

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    autoamate a door handle using vhdl or verilog

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