Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    115 jobs found, pricing in USD
    ASIC Design in Verilog 6 days left
    VERIFIED

    This project is related to Computational Neural Networks

    $69 (Avg Bid)
    $69 Avg Bid
    3 bids
    VHDL Radio clock 6 days left
    VERIFIED

    everything is going to be explained on the pdf

    $32 (Avg Bid)
    $32 Avg Bid
    6 bids

    I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card.

    $168 (Avg Bid)
    $168 Avg Bid
    4 bids

    My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa

    $128 (Avg Bid)
    $128 Avg Bid
    12 bids

    My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa

    $148 (Avg Bid)
    $148 Avg Bid
    10 bids

    refactor the sample code by using the c++

    $134 (Avg Bid)
    $134 Avg Bid
    8 bids

    I believe you must do this project.

    $127 (Avg Bid)
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    2 bids
    project for Ahmed M 5 days left
    VERIFIED

    I believe you must do this project.

    $155 (Avg Bid)
    $155 Avg Bid
    1 bids
    verilog project 5 days left
    VERIFIED

    want verilog code on fpga i want soon

    $8 / hr (Avg Bid)
    $8 / hr Avg Bid
    2 bids
    50 usd zynq verilog C project 5 days left
    VERIFIED

    50 usd Initial zynq verilog C project

    $46 (Avg Bid)
    $46 Avg Bid
    7 bids

    Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. We will need to discuss the project and its potential as there is opportunity here. If you have any question let me know.

    $17 / hr (Avg Bid)
    $17 / hr Avg Bid
    5 bids

    THis must implement on quartus( altera FPGA cyclone IV)

    $71 (Avg Bid)
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    3 bids
    making verlog hdl code 5 days left
    VERIFIED

    calculataion area in black and white image on fpga ( cyclone IV)

    $124 (Avg Bid)
    $124 Avg Bid
    7 bids
    VHDL Coursework 4 days left
    VERIFIED

    help in VHDL codes ,, everything will be explained later

    $56 (Avg Bid)
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    11 bids
    fpga software 4 days left

    I want to read programmes in FPGA chips

    $413 (Avg Bid)
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    17 bids

    je suis suposé faire un projet en VHDL de A jusqu'à Z , je manipule bien le logiciel je peux decrire aussi que simuler et implémenter sur une carte FRGA , mais je me crois pas au niveau pour bien choisir un sujet ( je suis débutant , je connais pastrop sur ce que peut faire ce merveilleux logiciel ) aussi que faire l'architecture globale du projet

    $134 (Avg Bid)
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    4 bids

    using Verilog which will be able to communicate with the memory of the processor

    $63 (Avg Bid)
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    3 bids
    simple verilog hdl code 3 days left
    VERIFIED

    calculate each area in black and white image

    $41 (Avg Bid)
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    10 bids
    Simple Verilog Project 2 days left
    VERIFIED

    Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3.

    $20 (Avg Bid)
    $20 Avg Bid
    7 bids