Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

Filter

My recent searches
Filter by:
Budget
to
to
to
Type
Skills
Languages
    Job State
    13 jobs found, pricing in USD

    I need to have a high level synthesis c++code to synthesis in vivado for hardware implementation in FPGA.

    $56 (Avg Bid)
    $56 Avg Bid
    2 bids
    VLSI Project -- 2 6 days left
    VERIFIED

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. Check the following link. [login to view URL]

    $240 (Avg Bid)
    $240 Avg Bid
    1 bids
    A vlsi design 5 days left

    magic design on ubuntu where you can build

    $26 (Avg Bid)
    $26 Avg Bid
    1 bids
    VLSI Project 5 days left
    VERIFIED

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. Check the following link. [login to view URL]

    $247 (Avg Bid)
    $247 Avg Bid
    3 bids

    I need an expert who has excellent knowledge of Microprocessor and Operating System

    $74 (Avg Bid)
    $74 Avg Bid
    3 bids

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    $47 (Avg Bid)
    $47 Avg Bid
    5 bids

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting and growing Blockchain Technology + No cont...

    $16 / hr (Avg Bid)
    $16 / hr Avg Bid
    7 bids
    Vivado HLS Expert 3 days left
    VERIFIED

    I am willing to pay for only Vivado HLS expert. Will discuss via interview.

    $1345 (Avg Bid)
    $1345 Avg Bid
    8 bids

    The project requires hardware & software design, implementation and testing of a simple & basic multi-function digital clock using Zynq 7000 ZED board. See attached for further information and specifications.

    $425 (Avg Bid)
    $425 Avg Bid
    13 bids

    i need to build a Gaussian elimination by MIPS

    $53 (Avg Bid)
    $53 Avg Bid
    13 bids
    FPGA with server 3 days left

    create a web api connect to the fpga cyclone v (altera de10-standred) , then altera can response to hte request change connect some point with each other.

    $547 (Avg Bid)
    $547 Avg Bid
    5 bids

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
    $104 Avg Bid
    4 bids

    General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Ba...

    $49 (Avg Bid)
    $49 Avg Bid
    9 bids