Design of dual port ram having each port with different clocks and write enable of 4 [login to view URL] the 23 states marching algorithm of the bist controller rtl this dual port ram should be instantiated then for this module verifcation should be done using UVM methodology or system verilog .with the insertion of MBIST how the verfication must be done for memory module
should develop SPI single master-single slave verification IP using UVM and verify different test scenarios. should mimic the BFM design in driver without using DUT and verify all the modes of SPI and some error conditions and create coverage statistics for the verified module.
MESI is a cache coherence protocol. The verification of the protocol is to be done using System Verilog and UVM. The signals to verify is sent through the sequencer to the driver and through the virtual interface to the DUT. The assertion checks should be written in the testbench.