Design and testing the synthesis

Completed Posted Oct 29, 2014 Paid on delivery
Completed Paid on delivery

Build on the VHDL and Verilog logical structures . Both combinational logic and synchronous system design is included. NO required to synthesize the design but, should ensure that all your non-testbench code is synthesizable. Functional (i.e. behavioural) simulation of your test benches must be used to

verify your designs.

The developing & simulating should using the Xilinx ISE suite of tools.

Some of these methodsare required to implement some of these functions into a flexible 16-bit cryptographic co-processor:

• Substitution.

• Permutation.

• Key Addition.

• Addition over a finite field.

• Multiplication over finite field.

The structure of the project is as follows:

Section 1: Designing of the combinational components which are utilised in our crypto-processor.

Section 2 :Synchronous designs, as well as the components needed to ensure the data processed by our

combinational logic can be stored.

Finally , a test program is given to ensure the final synchronous design works as expected.

Software Architecture Verilog / VHDL

Project ID: #6658463

About the project

2 proposals Remote project Active Oct 29, 2014

Awarded to:

loi09dt1

Let's discuss the fee you want. I will do it for you soonest and cheapest. I have had 2 years experiencing on FPGA design using Verilog and VHDL. Now I'm working with VHDL and Verilog everyday. That's why I'm the idea More

$66 USD in 1 day
(3 Reviews)
2.1

2 freelancers are bidding on average $71 for this job

SqUa11

Hello, I am expert in Verilog. I checked your project I can handle it. but ur budget is very low for it. Could you contact me for negotiation? Regards

$75 USD in 1 day
(2 Reviews)
2.3