I have a number (3) of Verilog files that need to be converted to VHDL, they are not particularly complex, in fact one could be converted in under 10 seconds.
I then need the converted files tied into another VHDL UART communication program & CLK
The Input/output for the existing VHDL is very close to the Verilog Input/output
The output for the Verilog *might* need splitting down from 127bits to 4 lots of 32 bits then stuffed into a FIFO for the Existing VHDL to take care of.
Target device is a Virtex5
The final job must be able to IMPLEMENT & synth. the logic for the required device
There is other work related to this project if it works out...
Please DO NOT apply if you are an Ex- C++ programmer who thinks they can program in HDL.
Hi, I'm really interested in implementing your project. 14+ years experience in Verilog coding, 12+ years in VHDL, 10+ in FPGA realization of Verilog/VHDL designs.
I am an Electrical Engineer and I did my final year project which involved a lot of conversion from VHDL to Verilog and vice versa. I can do it for you.
I have implemented H.264 video codec core in verilog .I am excellant with Xilinx Virtex 5 FPGA and Altera Cyclone 2. I am capable to provide a fully synthesizable core for these boards.