Hi,
I have experience from coding to generation of binary file that configures the PLD / FPGA.
I can code in verilog, VHDL.
The circuits that i have implemented in verilog is described briefly as follows
1.
Debounce circuit which does the function of CPU in accepting the input sensor value (1 or 0), debounce of the 16 bit input and delivering to the software interface (Local bus).
2.
Circuit functioning as CPU that controls and interfaces software (local bus) to DPRAM.
sending data to DAC.
3.
glue logic interfacing the CPU and ICs involved in power bring up.