In this project, you are required to develop a structural Floating-Point Unit (FPU) for use with a microprocessor. The processor needs to be capable of floating point addition and multiplication. The numbers are to be encoded into IEEE 754 single precision 32-bit format. The FPU should also be able to detect and flag the 'NaN' cases.
For the project demonstration, interface the FPU to the DE-10 RAM and perform the operation A*B+C on 1000 data triplets (A, B, C). Transfer the results back to the RAM, then upload to the PC for display. Verify the results by comparing them with another method (e.g., C program, spreadsheet etc.). This project Must be built using Quartus Prime's Verilog code. A code example is attached, you can follow the example but please modify it to fit my project description.
3 freelancers are bidding on average $192 for this job
Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 5 years. I did similar projects as well. Please let me know if the requirement is still there I can do the work. Thanks