DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS
Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero
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hello dear!I am interested in your project. Relevant Skills and Experience electronic , control engineering Proposed Milestones ₹27777 INR - finish I can do it well.