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DDR SD ram controller

DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS

Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero

Skills: Electrical Engineering, Electronics, FPGA, Microcontroller, Verilog / VHDL

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About the Employer:
( 0 reviews ) India

Project ID: #15826487

11 freelancers are bidding on average ₹28737 for this job

₹27777 INR in 10 days
(317 Reviews)
7.6
eopskzs

DDR controller core will be generated for selected Xilinx FPGAs as requested in project description. A report will than be generated and simulation results will be shown in ModelSIM. Relevant Skills and Experience Xil More

₹25000 INR in 12 days
(2 Reviews)
4.1
trutony

hello dear!I am interested in your project. Relevant Skills and Experience electronic , control engineering Proposed Milestones ₹27777 INR - finish I can do it well.

₹27777 INR in 10 days
(6 Reviews)
3.7
vlsirajagopal

DDR SDRAM design verification using standard EDA tool and language.(verilog/system verilog). Relevant Skills and Experience Having more than 6 years industry experience in writing verilog/systemverilog design and DV. More

₹36666 INR in 10 days
(5 Reviews)
3.5
alinayyar

Dear, We will use xilinx and verilog for coding purposes. We will give RS-232 interface for sending and receiving data to and from FPGA board. Regards, Relevant Skills and Experience 7+ years experience in Rnd Organiz More

₹27777 INR in 10 days
(2 Reviews)
1.5
hammadsamikhan

I have more than 4 years experience in fpga Ip core development

₹33333 INR in 10 days
(2 Reviews)
0.6
chanchal6891

A proposal has not yet been provided

₹27777 INR in 10 days
(0 Reviews)
0.0
ubtblr

Please refer to [login to view URL] for our experience/expertise and academic background. We are experts in hardware/software design/development. Relevant Skills and Experience hardware/software design/development. Ex More

₹27777 INR in 15 days
(0 Reviews)
0.0
hungfreelancer

I have 10 years of experiences in design and verify using Verilog and SystemVerilog HDL. I have experience of using DE1, DE2 (Altera), Virtex7(Xillinx),.. Please choose me. Best Regards. Relevant Skills and Experience More

₹15555 INR in 10 days
(0 Reviews)
0.0
₹44444 INR in 10 days
(1 Review)
0.0
alexstyle

D velopement environment xilinx ise and simulation Isim or modelsim. You need to create your own customized ipcore ?

₹22222 INR in 10 days
(0 Reviews)
0.0