I have project in which I required the following parts to solve,
1) a state diagram for modeling the system as an FSM (finite-state-machine). Specify in the Sketch same sketch the meaning of each state, the input(s) and output(s).
2) Design the FSM using Verilog code and simulate the FSM. (Use comments to indicate the meaning of each variable.)
3) Write a report to explain in detail the state diagram, FSM design source code, and simulation result. Summarize the project in the report
Furthermore, you have to use simulation on vivado for this project.
Do you able to do this please see the attachment?
7 freelancers are bidding on average $37 for this job
hi, I will work on this in a day and will be ready with VIVADO simulations for your target technology in no time. I have experience in both FSM design and Verilog since its the only two works I do.
I am an Electronics Engineer. I have experience with xlinx fpga verilog programing. I am confident i can deliver you this project. If you like you can discuss any ambiguity in chat.