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Verilog Task with Icarus Verilog

$10-30 AUD

In Progress
Posted over 5 years ago

$10-30 AUD

Paid on delivery
ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG
Project ID: 18055403

About the project

9 proposals
Remote project
Active 5 yrs ago

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$30 AUD in 1 day
0.0 (0 reviews)
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9 freelancers are bidding on average $31 AUD for this job
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Dear sir I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss Best regards
$30 AUD in 1 day
4.9 (463 reviews)
8.0
8.0
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A highly-skilled FPGA engineer with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, PLP Tools, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, CMOS VLSI Design, Cadence Virtuoso, Layout XL, Digital IC Design from RTL to GDSII, Analog IC Design.
$25 AUD in 1 day
4.9 (130 reviews)
6.6
6.6
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Hello! Please check my profile and reviews to know a bit about me and my work. It would be great if I could help you out.
$25 AUD in 1 day
4.9 (84 reviews)
6.3
6.3
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Can you please share the specs of ALU you want? and the simulation details. I have already designed many ALU's. It can be completed within no time.
$55 AUD in 1 day
5.0 (1 review)
2.2
2.2
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Throughout my education years, I have designed many processor datapaths and a CPU. My CPU was handling 8-bit applications such as text parsing, n-long array computation and etc. While doing those projects, I have already designed ALU blocks in VHDL. I can easily covert them into verilog. Moreover, I am writing systemverilog code everyday while i am completing the FPGA verification tasks. Therefore, I believe that my skills are totally compatible with the requirement of yours. I look forward to hear from you.
$28 AUD in 1 day
0.0 (0 reviews)
0.0
0.0
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I have 13 years of professional experience in digital design and verification. So I can write the code for ALU in Verilog and simulate and verify it using Icarus Verilog.
$25 AUD in 1 day
0.0 (0 reviews)
0.0
0.0
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Please share the details of the project. I am highly experienced in working on projects relevant to Verilog HDL and implementing them on FPGA development boards.
$25 AUD in 1 day
0.0 (0 reviews)
0.0
0.0

About the client

Flag of INDIA
Nagpur, India
4.9
77
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Member since Jul 31, 2013

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