VLSI Design For Low PDP Domino Logic

Title: Research & Implementation Requirement – Ultra Low PDP Domino Logic Design for IEEE Publication Project Objective I need an experienced VLSI Research Engineer with expertise in Cadence Virtuoso, Spectre Simulation, CMOS Circuit Design, Low-Power VLSI, and IEEE Paper Writing. Reference Paper: "Reduction of Variation and Leakage in Wide Fan-in OR Logic Domino Gate" (Integration, VLSI Journal, 2023). Tasks Phase 1: Literature Study 1. Study and implement all major domino logic designs mentioned in the reference paper. 2. Recreate the following circuits: - Conventional Domiof given paper Gate (CDG) - SARDDG - HSCDDKDG - RVLDG (Reference Proposed Design) - Any additional recent low-power domino circuits (2023–2026) 3. Verify all designs using Cadence Virtuoso and Spectre Simulator. Technology Requirements • Technology Node: 90nm CMOS (preferred) • Supply Voltage: 1V • Simulator: Cadence Spectre • Tool: Cadence Virtuoso • Temperature Analysis: - -50°C - 27°C - 100°C Required Measurements 1. Average Power 2. Propagation Delay 3. Leakage Power 4. Power Delay Product (PDP) 5. Noise Margin 6. Monte Carlo Variation Analysis 7. PVT Analysis 8. Area Estimation 9. Figure of Merit (FOM) Main Goal The primary objective is to design a novel domino gate with the LOWEST PDP among all existing designs. The design should outperform: - Conventional Domino Gate - SARDDG - HSCDDKDG - RVLDG Novelty Requirements I do NOT want a simple reproduction of the paper. The freelancer must propose a NEW architecture with clear novelty. Expected Benefits: • Lower Dynamic Power • Lower Leakage Power • Reduced Delay • Improved Noise Margin • Better Process Variation Tolerance • Minimum PDP Optimization Target The proposed design must achieve: PDP(Proposed) < PDP(RVLDG) Target improvement: •lower PDP than RVLDG. • Maintain full swing output. • No logic degradation. • Stable under PVT corners. Deliverables 1. Cadence Virtuoso Schematics 2. Spectre Netlists 3. Testbenches 4. Simulation Results 5. Waveforms 6. PDP Comparison Tables 7. Monte Carlo Analysis 8. PVT Analysis 9. Layout (optional but preferred) 10. IEEE Conference Paper IEEE Paper Requirements Paper should contain: 1. Abstract 2. Introduction 3. Literature Review 4. Research Gap 5. Proposed Architecture 6. Mathematical Analysis 7. Simulation Setup 8. Results & Discussion 9. PDP Comparison 10. Conclusion 11. References Publication Target IEEE Conference / IEEE Xplore Indexed Journal. Important Requirement The novelty must be genuine and technically justified. The proposed architecture should be optimized primarily for minimum Power Delay Product (PDP), while maintaining full-swing output and low leakage power. All claims must be supported by simulation results and comparison tables.

Project ID: 40522516