i have a verilog code which has an error where a for loop and is not not working properly inside the main code but woking properly outside the main code

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Hi, I am Mtech graduate from IIT Roorkee and working on Verilog and VHDL for the past 3 years. I have done a course on Advanced Digital System Design. I have done many Digital system design projects using RTL design and FSM. As a part of my Mtech project i have written VERILOG code for virtual synchronous generator. As i am new to freelancing, money is not my concern but what i need is a good review. This is going to be my first project in freelancer and i promise to help you in the best as per your need in less time. Thanks

Hi, I am an Electronics and Telecommunication Engineer with my PG specialization in VLSI Design and Embedded Systems. I have an experience and have completed many projects in VLSI Design, Image Processing and Signal Processing. My VLSI Design skills include HDL programming using Verilog and SystemVerilog, RTL design and Simulation. Hope we meet at the chats. Thank you.