Job Description :-
We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs. The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating and Power-gating etc.
The work is in an advanced prototype stage and we plan to launch a product down the line. The team has people with chip-design experience in MNCs over decade and background of colleges as Indian Institute of Technology.
Job Requirements :-
1) We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and Architecture Specs.
2) The person needs to have an excellent/good Verilog/SystemVerilog/Perl [login to view URL] coding will be Perl mixed Verilog/SV.
3) Knowledge of Make, Python, Bash is an advantage, but not mandatory.
4) The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.
5) The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.
Who can Apply :-
1) Fresher/junior engineers looking for an opportunity.
2) People looking for training/upscaling in the domain can apply.
3) People looking to explore in-depth from scratch ASIC design can also apply.
1) Opportunity to work in complex ASIC product design from scratch.
2) Opportunity to learn alongside experienced and passionate engineers.
3) Monthly Stipend/Remuneration.
4) Facility to work remotely.
How To Apply :-
Please apply answering below points -
1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert.
2) Which area between design/verification you are more interested in.
Placeholder budget/timeline. Details to be discussed.
If you are sending a proposal, please be available in chat so that details can be discussed.