compression and decompression vhdl code

$30-250 USD

Closed

Posted

over 3 years ago

$30-250 USD

Paid on delivery

Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to decompress the data received in the ground station, then it will be analyzed in the computer. The proposed data compression in this work is the LZ data compression algorithm

Verilog / VHDL

Matlab and Mathematica

Electrical Engineering

C++ Programming

FPGA

Project ID: 28922306

About the project

4 proposals

Remote project

Active 3 yrs ago

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4 freelancers are bidding on average $170 USD for this job

@rizwanmpec

Expert in Cadence, T-Spice, P-Spice, Communication protocols. Assembly programming, FPGA, Enbedded etc. I can do this work. Pls send a msg to discuss further.

$140 USD in 7 days

4.9

(21 reviews)

4.6

@taamouchabdelhak

I think my bide is late but i am a VHDL developer and I can do this task. in Fact i have worked on Similar projects and I can do this task perfectly. Contact me

$200 USD in 7 days

5.0

(1 review)

1.8

@geekypolo

I read your job description and wish to contribute to it based on skills as an Electronics and telecommunication engineering student. I believe that my skills in VHDL and MATLAB will be immensely helpful for the task.

$89 USD in 15 days