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H.264/H.265 decoder

10 freelancers are bidding on average $4622 for this job

ahmedmohamed85

Dear sir I have more than 10 years experience in digital systems design using vhdl and verilog, please check my profile, also please message me so that We can discuss Best regards

$5555 USD in 30 days
(356 Reviews)
7.7
$5555 USD in 30 days
(2 Reviews)
4.1
$5555 USD in 30 days
(17 Reviews)
4.1
MUhammadt429i

Hello , how are you? Hope all is fine ! Regarding your project I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC.I use Quartus II and Vivado IDEs accordingly. I test More

$3333 USD in 30 days
(10 Reviews)
4.0
$4444 USD in 30 days
(2 Reviews)
3.0
Manoj3050

Hi, I'm an electronic engineer with more than 5 years of experience in Digital system designing. Currently I'm working for leading EDA company in silicon fabrication and I'm very good at Verilog designing. Also I ha More

$4444 USD in 30 days
(2 Reviews)
2.1
sky19130

Hello. i am electrical engineering expert and i have good skill in firmware programming such as vhdl , verilog, assembly .. i will do my best and you will get good result thank you

$4444 USD in 60 days
(2 Reviews)
0.9
CapaIT

I'm an Electronics and Telecommunications Engineer having a master degree in EE. I have experience in design and implementation of electronics projects. In a related work I have wrote a VHDL code H264 video compression More

$4444 USD in 30 days
(0 Reviews)
0.0
Piao217

I have rich experience about VHDL/FPGA. And I have made VHDL codes which compress and transmit/receive from HD video to H.264 using Vertex 6 FPGA. In order to complete this project, I just have to modify some parts o More

$4000 USD in 30 days
(0 Reviews)
0.0
NienYi07

I am in hardware asic designer working on algorithms and packet checking for firewall asics in Silicon valley. Extensive knowledge designing, debugging, running simulations and closing timing for ASIC design flow. Fami More

$4444 USD in 30 days
(0 Reviews)
0.0