Design a 8-bit MPZ using HDL description
$10-30 USD
Paid on delivery
The conventional (single-match) priority encoder finds only one match, i.e. the highest priority input.
An n-bit MPZ unit finds r (1 ≤ r ≤ n) matches in exactly r cycles.
Design an 8-bitMPZ using HDL description. You may use ModelSim or Quartus II software. In
your implementation, you may have a mix of behavioral and structural descriptions for
modules/components. Slight modifications of the unit, compared to those provided in Section III
are allowed.
Your report for this problem should include the HDL code of your MPZ design and
simulation results to show the correct behavior, or any other interesting observation (e.g.
maximum clock frequency of the design).
Project ID: #15113656
About the project
8 freelancers are bidding on average $37 for this job
I think you want Multi match Prioritizer unit as mentioned in the IEEE paper "Customised TCAM architecture for multimatch packet classifier". A verilog code for the same I can give in 2 days. Relevant Skills and Expe More
I can do a synthesizable code for a specific architecture. synthesis and Implementation in Altera Quartus Do you have any specific architecture?
Will be able to complete in 3 days once stated requirement are clear. Will be delivering VHDL code along with testbenches and Vivado simulation result. Relevant Skills and Experience VHDL, Xilinx Zynq series and spart More
