Europe, Italy timezone preferred.
Lead the activity for porting FPGA design to Silicon technology (memory replacement, ...)
Carry on simulations of the updated RTL design to check that the functionality remains unchanged
Execute static and formal verification of RTL code using appropriate tools
Run trial synthesis on the RTL design and check the timing violations
Lead the activities for SoC sub-block Static Timing Analysis.
Required Skills (expert):
VHDL language
Digital ASIC design flow
Use of digital simulations with standard industry simulators (Mentor QuestaCore)
Static and formal RTL verification (e.g. Synopsys Spyglass)
Synthesis tools (e.g. Cadence Genus)
UVM and System Verilog test benches