Hi , we need help debugging and implementing stalls and data forwarding for a 5 stage pipelined [login to view URL] processor uses RISC-like instruction set. The processor has four internal registers: R0, R1, R2, and R3. Each register is 1-byte. The address space of instruction memory and data memory is 256, and the processor uses little-endian byte ordering. The length of all instructions is the same and is 2-byte.
I am done with most of the coding but processor is not giving the output, we have very limited time of 24 hours for this