Xilinx Spartan 6 Verilog USART

I need a Verilog USART code to work in a Spartan 6 FPGA. The USART need be: Start bit + 8 Data Bits + even parity check + 1.5 Stop bits . The 1.5 stop bits is to implement an error detection, you don't need do anything with this just take 9th(parity) and 10.5(error detect) bits as part of the data, the upper function check parity and error, from 10.6 time cud be consider as next byte. The speed shod giving in a CLK input signal, the Data out should be a 10 Bits array (8 Data + Parity + Err detect). Should be similar to the Xilinx USART_RX KCPSM6 but with no buffers and with Parity + 1.5 Stop bits. The most important part are the noise filter, I have my own code already done for this and work 99% error free but I need 100% error free with noise then PLEASE DON'T BIT IF YOU ARE NOT AN EXPERT.