Sachin S M. Profile

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$10 USD / hour

bangalore,

india

$10 USD / hour

It's currently 2:18 PM here

Joined April 29, 2020

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Sachin S M.

@SachinSMBnglr

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$10 USD / hour

bangalore,

india

$10 USD / hour

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FPGA Design Engineer

I am a dedicated FPGA RTL Design Engineer from Bangalore, India. I have working experience on FPGA on Xilinx ISE & Vivado platforms using Verilog/VHDL. I have worked on applications of Image/Video/Speech Processing, Cryptography, Steganography, AES, Network-on-Chip, UART, SPI, I2C, etc. I can work on Matlab, Simulink and System Generator and Chipscope tools. Eager to learn new concepts and work on advanced projects with supportive team and work for mutual development as a individual and inside organisation.

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Experience

Bangalore

Jul 2017 - Present

I have working experience on FPGA on Xilinx ISE & Vivado platforms using Verilog/VHDL. I have worked on applications of Image/Video/Speech Processing, Cryptography, Steganography, AES, Network-on-Chip, UART, SPI, I2C, etc. I can work on Matlab, Simulink and System Generator and Chipscope tools.

Education

B.E in Electronics and Communication Engineering

Visvesvaraya Technological University,

India

2013 - 2017

(4 years)

Publications

Performance of Median Filter and its Variants for the Preprocessing of Mammilia Cancer Imagery

International Journal of Innovative Technology and Exploring

The project aims at designing the algorithm for early stage detection of breast cancer. The published paper is the work of implementation and testing the results of preprocessing of breast cancer images with different filter variants like Median Filter (MF), Adaptive MF, Progressive Switching MF and Relaxed MF. The algorithms are implemented on MATLAB 2018.

An FPGA Implementation of 2D Filter using Vedic Multiplier

International Research Journal of Engineering and Technology

The project aims at implementing of 2D filter for image pre-processing using Vedic multiplier technique in a 32bit RISC CPU design. The design is coded using VHDL script on Xilinx ISE 14.5 and the hardware module is built using Simulink in MATLAB 2012(a) and Co-simulated using System Generator on Spartan 6 Digilent Atlys FPGA Development kit.

Design and Implementation of Efficient Histogram Equalization in FPGA

International Research Journal of Engineering and Technology

The project aims at implementing an area and speed efficient architecture of Efficient Histogram Equalization. The design is coded using VHDL script on Xilinx ISE 14.5 and the hardware module is built using Simulink in MATLAB 2012(a) and Co-simulated using System Generator on Spartan 6 Digilent Atlys FPGA Development kit.