Chethan Kumar H. Profile

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$12 USD / hour

singapore,

singapore

$12 USD / hour

It's currently 2:12 PM here

Joined April 7, 2019

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Chethan Kumar H.

@chethank2807

0.0

(0 reviews)

0.0

$12 USD / hour

singapore,

singapore

$12 USD / hour

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Digital design engineer with teaching experience

I have 8+ years of experience in digital/FPGA/ASIC design and verification, I have guided a significant number of students on their university projects. Most of the projects were FPGA based. Since I have been working in the semiconductor industry for quite a long time and have written a significant number of blogs on various topics, I believe I can deliver the best when it comes to teaching, with great real-time examples and tutorials. I always believe in learning with live example and i apply the same while teaching. I have a habit of creating an online one notes for anything I learn so that it can be easily referred to when it is required. I advise the same method to anyone I am tutoring. My teacheron profile :- [login to view URL]

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Portfolio

6352573

MIPSfpga-NOC-overlay

6352569

Real-time-FFT-Spectrum-analysis

6352558

Decision-tree-based-denoising-method

6352573

MIPSfpga-NOC-overlay

6352569

Real-time-FFT-Spectrum-analysis

6352558

Decision-tree-based-denoising-method

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Experience

ST Microelectronics

Oct 2018 - Present

•Image signal processing digital IP design and verification. •Camera sensor SOC digital design, integration, and verification. •SOC lint and CDC checks. •Digital design flow automation and other design activities

Hewlett Packard Enterprise

Jun 2016 - Oct 2018 (2 years, 4 months)

• Microarchitecture FPGA components of network switches • FPGA logic development, implementation, functional & timing simulation. • Formal verification of critical IPs on jasper gold tool • Integration of custom logic, generated IP cores and hard IP blocks to meet system requirements. • CPLD and Reusable IP development. • Script development for testing FPGA modules on hardware

Nanyang Technological University, Singapore

Oct 2015 - Apr 2016 (6 months, 1 day)

•RTL Development and testing of deflection torus multi-layer NOC (Network on hip). •Added new set of customized instructions (SEND/RECEIVE) to the mipsfpga soft processor to support direct data transfer between the processors •Building 256-core microAptive MIPS overlay for FPGA’s using MIPSfpga soft processor and establish communication among the processors through NOC. •Implementation of Real Time Audio Spectrum display on ZedBoard

Education

Masters in embedded systems

Nanyang Technological University,

Singapore

2015 - 2016

(1 year)

Publications

Deflection Routing for Multi-Level FPGA Overlay NoCs

publication descriptionInternational Conference on Field-Programmable Technology

we design a deadlock-free hierarchical torus that (1) targets worst case latencies in deflection torus NoCs by separating deflections into two levels of the NoC, (2) delivers an FPGA-friendly design for deadlock freedom by providing physical escape channels in the lower levels, and (3) naturally supports physical layout for large multi-die FPGA chips by mapping upper level links to expensive interposer connections between dies.

Publications 120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board

publication descriptionInternational Symposium on Field-Programmable Gate Arrays

Design a 120-core 94MHz MIPS processor FPGA over-lay interconnected with a lightweight message-passing fabric that fits on a Stratix V GX FPGA (5SGXEA7N2F45C2). We use silicon-tested RTL source code for the microAptiv MIPS processor made available under the Imagination Technologies Academic Program. We augment the processor with suitable custom instruction extensions for moving data between the cores via explicit message passing.