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riyadh, saudi arabia
It's currently 3:39 AM here
Joined April 30, 2024
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Riyane S.
@sidlakhdar
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riyadh, saudi arabia
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Senior IT and digital consultant, PhD
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Experience
Senior Associate Consultan
Jul 2022 - Jan 2024 (1 year, 6 months)
- Managed projects designing and executing data and AI strategies for top financial institutions in Europe and North America.
- Led teams in engineering, consulting, and deploying a core computing tool (Python/Polars, AWS) to assess credit-risk for a major French investment bank.
- Advised senior leadership of a major financial institution in North America on AI solutions and cloud-based optimizations for operational efficiency and cost saving.
Senior Associate Consultant
Jul 2020 - Jul 2022 (2 years)
- Helped Natixis unlock 4% uplift in revenues by designing a smart digital-pricing strategy for its financial products (Forex and Interest-Rate markets)
- Led a team of 2 Data analysts to drive the implementation of the pricing solutions
Software Engineer
Dec 2017 - Jul 2020 (2 years, 7 months)
- Within the OPRECOMP EU project, created a programming framework to optimize large-data placement
- Registered two international patents on the consequential findings derived from the project
- Supervised a team of 5 software engineers in developing a C/C++ compiler implementing the solutions
Education
Doctorate
(3 years)
Masters
(2 years)
Publications
Methodology for code-optimization of memory data layouts by adaptation to HPC-system architectures
theses.hal.science
In this thesis, we plot a first step toward automatic software-adaptation to hardware. We present an iterative data-mining-related software optimization approach based on the detection and the exploration of the most influential parameters linked to the hardware, operating system and software.
On the Impact of Asynchronous I/O on the performance of the Cube re-mapper at HPC Scale
Julich Supercomputing Center
In this paper, we considers enhancing the I/O-access of the Cube re-mapper, a state-of-the-art trace-analysis software for HPC executions. We propose an overlapping-I/O write approach to outperform the time-response of the Cube re-mapper. Thanks to a theoretical study of the general pattern followed by the Cube re-mapper, we show that our method may bring an improvement up to 75% on this pattern.
Toward Modeling Cache-Miss Ratio for Dense-Data-Access-Based Optimization
ACM - Embedded System Week (EsWeek)
This allows to benefit from processors that are primarily designed to improve system performance. To reach such a software/hardware fitting without narrowing the scope of the optimization to few executions, one needs to have at his disposal relevant performance models of the considered hardware. This paper proposes a new method to optimize software kernels by considering their data-access mode. The proposed method permits to build a data-cache-miss model of a given application.
Data-layout optimization based on memory-access-pattern analysis for source-code performance improv
ACM - Proceedings of the 23th International Workshop on Software and Compilers for Embedded Systems
With the rising impact of the memory wall, selecting the adequate data-structure implementation for a given kernel has become a performance-critical issue. This paper presents a new methodology to solve the data-layout decision problem by adapting an input implementation to the host hardware-memory hierarchy. The proposed method automatically identifies, for a given input software, the most performing data-layout implementation for each selected variable by analyzing the memory-access pattern.
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