UART Core Verification
Functionally Verified UART core using SV/UVM.
About Me
7 yrs of experience in FPGA/Asic design and verification domain verilog/VHDL,system verilog,UVM,OVM,VMM . Working on Spartan 3 and Altera DE1 SOC FPGA boards Worked on tools: Xilinx ise Quartus modelsim questasim VCS Matlab Other skills: C,C++,shell scripting,perl expertise in IP/SOC level design Verification worked on functional verification of various blocks in four ARM based SOC designs worked on Designing SPI,I2C,AHB to APB Bridge,PCS layer 1 gigabyte wokred on AHB,AXI,APB,DDR3, Design verification
