Error Emulation model

Completed Posted Mar 1, 2016 Paid on delivery
Completed Paid on delivery

design a structural 16-bit floating point adder and integrate it with error-injection model(VHDL)

Verilog / VHDL

Project ID: #9815586

About the project

1 proposal Remote project Active Mar 2, 2016

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$250 USD in 1 day
(213 Reviews)
7.4