This project consists to port some c code (around 50 lines) to Verilog in order to run on a FPGA.
Output of the contest
Verilog .v source file equivalent of verilog.c
testbench .v file equivalent to doSimulation()
You can run the C code with "gcc main.c && ./[login to view URL]"
Elements to select the winning bidder:
- Partial screenshot of the implementation or snipset of the implementation
- Any ideas, comments, remarks how to get the best implementation
- How MIN2 and MAX2 is implemented
- Approximate number of LUTs of the module
- If a Lattice Diamond project is provided for the simulation. I use Lattice which is freely available at [login to view URL] (including the simulator)
- The code has been tested on a simulator (required)
- The code has been tested on a FPGA (optional)
- CV and resume of the bidder
I'm an experience hardware developer in the SF bay area. Worked on low level firmware programming using C and also have extended simulation and bringup experience coding in Verilog. Work daily on running simulations and estimating hardware cost and getting hardware to be cost efficient and working. A good communicator that strives to deliver on time, on budget.
$50 USD in 3 days
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2.7
5 freelancers are bidding on average $58 USD for this job
Dear sir
I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss
Best regards