UVM Expert Required - Design Verification

I have around 3yrs of experience in UVM. I have developed different testbench in UVM. I have worked for all the components.

Hi there, i thoroughly went through your project description. I'm an expert and I can help. Kindly Please kindly send me a message. I'm a senior engineer with rich experience in Verilog / VHDL, Very-large-scale integration (VLSI), C Programming, Python, Algorithm, Machine Learning (ML), Deep Learning. I am a Python developer with 5+ years of experience Skills: PyQt, PySide/PyQt,Scrapy, BeautifulSoup Java, C++, C#, SQL, 4, Pillow, Matplotlib, Xml, PHP, Django json, and csv modules. Expert in statistical analysis of datasets/images and apply ML/DL algorithm with python (Tensorflow, Keras,Pytorch) and R. I am interested in taking this task up for you and I hope I could awake your interest in me. Please kindly send me a message in chat window for more about the project and to adjust price, note price quoted in bid is not the final price, it can be less or more after discussing the project. I am always online, work hard and very sensitive to details. I hope to read from you in chat box. Best regards

I'm a Verification Engineer specialized in UVM and Formal Verification. I have experience working with international companies developing their testbenches using different EDA tools. I checked the spec that it has I2C Communiction module. I have worked on other communication protocols such as PCIe. I have worked on other UVM Environments. Please let's discuss the requirements needed in person