SPGA code for pulse generation

I had 8+ years of experience in the field of FPGA, VHDL and Verilog HDL. I also have the Spartan 6 FPGA board. I can do this task for you.

A proposal has not yet been provided

A proposal has not yet been provided

Hi i am having 10+ years of experience in the same arena, please let me know how to take this further , I am ready to provide competitive bid and provide complete support on whatsapp and skype thanks SK

My solution will be based on simple counter. The counter divide input clock signal to 50 Hz pulses with 10% duty cycle. The 0,01s delay is unclear to me - is it delay to some other signal? There will be test bench in my solution as well.

Hello Sir, Please go through my profile or chat with me for more information. I am looking forward an opportunity to work with you. Thanks Luffy08

A proposal has not yet been provided

I am a 4th year undergraduate electrical engineering student at Carleton U. I am currently taking my 2nd course on VHDL. With more specific details on the coding requirements (if anymore than whats given in the description), I am 100% confident I can complete the coding. I am also willing to negotiate my bid.

Hello, I am new on this site but I have good experience with VHDL language from college. Let's talk about the project and I'll assure you that you will get what you want at the lowest price. Thank you for your time.