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    2,000 vhdl jobs found, pricing in USD
    IP Integrator with Basys 3 Digilent Ended

    Program the Basys 3 using the Cordic IP Integrator to generate: the hyperbolic sine and hyperbolic cosine of an angle parameters: You must enter the angle in degrees using the switches, so that the vhdl code includes its respective conversion to radians. This angle should be shown on the 7 segment displays. Pressing btnu the displays should then show the (hyperbolic sine) of the entered angle, and pressing btnd should show the (hyperbolic sine) of the angle.

    Electronics FPGA Microcontroller Verilog / VHDL
    $30 (Avg Bid)
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    VHDL Video Test Pattern generator Ended

    The company is searching for external collaborators to design and test a Video test pattern generator in VHDL. The module shall be configurable for different pixel bit, num,ber of pixel per clock, different pattern generated, resolution, frame rate, colour format, video output sequence

    Electronics Engineering FPGA Verilog / VHDL Video Processing
    $586 (Avg Bid)
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    17 bids
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    Design and Simulation of Combinatorial and Sequential Digital Systems Using VHDL Behavioral Modeling and the Xilinx Vivado Design Suite Ended

    1)Using VHDL and the Xilinx Vivado Tools, design and implement a 4-bit ALU whose functionality is compliant with the TTL MSI 74LS381A specifications. The design must use a VHDL behavioral modeling coding style and can include concurrent and sequential statement types. Source code modules must include liberal commenting to clarify and explain function and operation your code. 2) Create a test bench VHDL module and use the Vivado Simulator to test/verify proper operation of the ALU’s functions with all input data patterns specified in the 74LS381A functional table. Recommendation: to make comparison of simulated results to those listed in the functional table easier, apply the external stimulus input patterns in the same “row” order as inputs are listed...

    C Programming C++ Programming Electronics Microcontroller Verilog / VHDL
    $68 (Avg Bid)
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    13 bids
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    DO-254 Project VHDL Ended

    DO-254 Project - Task - Lint and Code coverage

    Analog Electronics Digital Electronics FPGA FPGA Coding Verilog / VHDL
    $181 (Avg Bid)
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    1 bids
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    Understanding of FPGA for a report Ended

    I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $73 (Avg Bid)
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    6 bids
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    Image processing using vhdl in Max V board ( quartus) Ended

    Image processing digital electronic system

    Electrical Engineering Engineering FPGA Matlab and Mathematica Verilog / VHDL
    $296 (Avg Bid)
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    9 bids
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    I have multiple tasks for Electrical Engineers Ended

    Hi, How are you doing. I am looking for electrical engineers to work on multiple tasks in following areas: • Embedded C Programming. • VHDL/Verilog, LABView/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. I am looking for long term work relationship. New freelancers are warmly welcomed. Important Note: I need dedicated freelancers who strictly follow the deadline and give me good quality work without any plagiarism.

    C Programming Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $149 (Avg Bid)
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    Expert on VHDL and FPGA (only expert required) -- 2 Ended

    I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

    Electrical Engineering Engineering FPGA Matlab and Mathematica Verilog / VHDL
    $140 (Avg Bid)
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    17 bids
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    XTEA Light Encryption-Decryption Engine Ended

    ...this project students are asked to implement a an XTEA Encryption/Decryption VHDL Engine, implemented in both C code and VHDL code. It supposed to be built as a custom hardware module and be interfaced to the NIOS II soft processor in the Alter- Intel Cyclone V FPGA chip [De-10Nano board]. The HDL code implements 2 number of pins: first an input from stdr_logic_vector type form of 32-bit length, and second an output with 32-bit of the same type. The Key is 32-bit in length, and they must be stored inside the VHDL code. The input reception and output generation may take multiple clock cycles or states but could be designed in less than that if was applicable. The internet could be surfed to lookup codes for both C and VHDL but the group is responsible to conve...

    C Programming C++ Programming Electronics Microcontroller Verilog / VHDL
    $492 (Avg Bid)
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    Vhdl projects Ended

    The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry,

    FPGA Verilog / VHDL
    $45 (Avg Bid)
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    Vhdl for video processing FPGA Ended

    We need a VHDL designer with expertise on video processing codec.

    Engineering FPGA Verilog / VHDL Video Processing
    $32 / hr (Avg Bid)
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    XTEA Encryption/Decryption VHDL Engine Ended

    Hello can you help me with this project it’s going to be similar to lab 4 that I have attached. I have attached the project pdf too ( 193.22 KB) this one Division.c #include "system.h" #include "altera_avalon_pio_regs.h" #include <stdio.h> /* register offset definitions */ #define DVND_REG_OFT 0 // dividend register address offset #define DVSR_REG_OFT 1 // divisor register address offset #define STRT_REG_OFT 2 // start register address offset #define QUOT_REG_OFT 3 #define REMN_REG_OFT 4 #define REDY_REG_OFT 5 #define DONE_REG_OFT 6 /* main program */ int main () { alt_u32 a, b, q, r, ready, done; printf("Division accelerator test #2: nn"); while (1){ printf "Perform division a / b = q remainder rn"); printf("En...

    C Programming Electronics FPGA Microcontroller Verilog / VHDL
    $620 (Avg Bid)
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    System Design and VHDL expert Ended

    System Design and VHDL expert for urgent Task

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $7 / hr (Avg Bid)
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    VHDL Project Ended

    The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019. To model analog and mixed-signal systems, an IEEE-standardized HDL based on VHDL called VHDL-AMS (officially IEEE 1076.1) has been developed.

    FPGA Verilog / VHDL
    $20 (Avg Bid)
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    Debugging VHDL code for Nios Processor Ended

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    Altera Quartus ASIC Digital ASIC Coding FPGA Verilog / VHDL
    $35 / hr (Avg Bid)
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    I need vhdl code Ended

    1010 sequence dectectorwith 20 bit frame with consecutively 3 frames with 16 bit payload and 4 bit header

    C++ Programming Electrical Engineering FPGA Microcontroller Verilog / VHDL
    $14 / hr (Avg Bid)
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    Project for Aamir Sohail N. -- 2 Ended

    Hi Aamir Sohail N., I noticed your profile and would like to offer you my project. We can discuss any details over chat. It is another VHDL Project I need implemented

    Electronics Engineering PCB Layout Powerpoint Verilog / VHDL
    $50 - $50
    $50 - $50
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    State Machine VHDL Ended

    Hi Daniel C., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    Algorithm C++ Programming Circuit Design Digital Design Electronics
    $50 (Avg Bid)
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    timing waveforms for vhdl code Ended

    I have vhdl code. i need timing waveform from modelsim .

    Electrical Engineering FPGA Matlab and Mathematica Microcontroller Verilog / VHDL
    $28 (Avg Bid)
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    Project for Mohan V. Ended

    I have a VHDL project available. I have a file that uses "process" that we want to rewrite in purely structural VHDL using components such as D flip flops and latches. Are you available for this task?

    Python
    $50 (Avg Bid)
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    Project for Sardar Hasnain A. Ended

    Hi Sardar Hasnain A., I have a VHDL project available. I have a file that uses "process" that we want to rewrite in purely structural VHDL using components such as D flip flops and latches. Are you available for this task?

    C Programming Electrical Engineering Electronics Engineering Microcontroller
    $50 (Avg Bid)
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    Write VHDL code for Vivado Ended

    I have a file in VHDL that I want to rewrite. The file uses "process" but we want to rewrite it using components. We have some of the modules you could use already written.

    Electronics FPGA Microcontroller Verilog / VHDL Very-large-scale integration (VLSI)
    $50 (Avg Bid)
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    single cycle mips processor with vhdl Ended

    Write the equivalent VHDL code, and Verify the correct operation through Vivado Simulator by comparing your simulation results with those of MARS runs.

    Digital Electronics Verilog / VHDL
    $77 (Avg Bid)
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    Develop a prototype using VHDL/FPGA Ended

    I want to create programming routines to be recorded on an FPGA

    Arduino Electronics FPGA Microcontroller Verilog / VHDL
    $33 / hr (Avg Bid)
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    Vivado software - FPGA Digital Systems -- 2 Ended

    Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $32 (Avg Bid)
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    Teaching Digital design using VHDL Ended

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    Altera Quartus ASIC Digital ASIC Coding FPGA Verilog / VHDL
    $16 / hr (Avg Bid)
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    Vivado software - FPGA Digital Systems Ended

    Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $39 (Avg Bid)
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    servomotor in vhdl Ended

    separate project in 3rd part, first make the chdl codes according to the state machine as well as their test ban (Reception and emission), make a top entity etc...

    Electrical Engineering Engineering FPGA Verilog / VHDL
    $43 (Avg Bid)
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    Expert on VHDL and FPGA (only expert required) Ended

    I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

    Electrical Engineering Engineering FPGA Matlab and Mathematica Verilog / VHDL
    $145 (Avg Bid)
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    I2C protocol implementation in VHDL Ended

    I want to use accelerometer sensor on FPGA, in order to do that I need I2C protocol implementation in VHDL so I can continue my work on the project. I want the module to get the address of the sensor + bit for R/W , and the internal register address of the sensor, and get the data by reading, or write to the register.

    Electrical Engineering FPGA Microcontroller Verilog / VHDL
    $260 (Avg Bid)
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    FPGA, Quartus , VHDL Ended

    Using the fixed point arithmetic measure current according to the following circuit

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $39 (Avg Bid)
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    VHDL Develop Project Ended

    Create a VHDL routine to water a plant using state machines and a specific board

    Electronics Engineering FPGA Microcontroller Verilog / VHDL
    $34 / hr (Avg Bid)
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    32 bit MIPS Processor Ended

    Instruction Decoder and ALU Control In this lab, students are expected to implement an instruction decoder and an ALU control unit using VHDL in the Xilinx software. The purpose of the instruction decoder is to generate proper control signals based on the Opcode of an instruction fetched from the instruction memory. The purpose of the ALU control is to set the proper ALU control signal based on the Funct field of an instruction and the ALUOp signal from the instruction decoder.

    C Programming Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $154 (Avg Bid)
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    FPGA designer in VHDL, DO-254 project Ended

    Good knowledge of VHDL is required. Libero Soc and Microsemi will be used The simulator will be Aldec Active-HDL, linting with Aldec Alint Design of a basic control board, standard interfaces, no high speed interfaces, no transceivers. DO-254 DAL C, basic knowledge is a plus some math algorithm in fixed point will be implemented on the hardware for motor control Supervision of our expert designers, short daily meeting and 1h weekly with reports on activities and scheduling contract will be extended month by month (we have budget for 6 months).

    DO-254 Certification FPGA Verilog / VHDL
    $297 / hr (Avg Bid)
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    Signal processing Using ML algorithm with (ZedBoard, VHDL, C and vivado) Ended

    1- Signal processing using ML on a computer (C Language) 2- using Single and dual ARM (C Language) 3-using FPGA Zedboard programmable logic (VHDL Language)

    C Programming DDR3 (PCIe, board design/fpga) FPGA FPGA Coding Verilog / VHDL
    $171 (Avg Bid)
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    c, vhdl expert needed -- 2 Ended

    i want code and report. I need plagiarism free report. software is quatrus

    C Programming C++ Programming Electrical Engineering FPGA Verilog / VHDL
    $6 / hr (Avg Bid)
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    c, vhdl expert needed Ended

    i want code and report. I need plagiarism free report. software is quatrus

    C Programming C++ Programming Electrical Engineering FPGA Verilog / VHDL
    $7 / hr (Avg Bid)
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    Improving upon a VHDL project Ended

    A VHDL project about producing Moors code and converting it to ASCI code needs to be improved since it does not produce correct results.

    Electrical Engineering Engineering FPGA Software Architecture Verilog / VHDL
    $184 (Avg Bid)
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    digital design using VHDL and VIVADO Ended

    Deadline is in 2 days Details will be trough the chat Please bid and I'll get back to u Thanks

    Electrical Engineering Electronics Engineering Matlab and Mathematica Verilog / VHDL
    $30 (Avg Bid)
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    VHDL and FPGA Expert Ended

    Need a VHDL and FPGA Systems expert 1. To create a modular system using VHDL. 2. To use simulation and test to verify the correctness of the design. 3. To demonstrate the milestones working on a target FPGA device. 4. To document the entire design process - recording the technical detail and justification of the work done. Detailed document will be provided on chat

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $151 (Avg Bid)
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    8x8 booth multiplier using vhdl Ended

    i have attached the specifics of the project. need to be finished by mid november

    Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL
    $487 (Avg Bid)
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    VHDL Expert Required Ended

    VHDL Expert Required Now Urgently

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $23 (Avg Bid)
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    6-bit division circuits for unsigned numbers using VHDL in the Xilinx software Ended

    I want to design and implement a 6-bit division circuits for unsigned numbers using VHDL in the Xilinx software.

    Computer Science Electrical Engineering Electronics Engineering Verilog / VHDL
    $120 (Avg Bid)
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    Implementación proyecto FPGA Ended

    Implementar, simular FFT en entorno aldec , bajo la plataforma Atlys Spartan-6. Simular e implementar FFT en dicha plataforma, desarrollar código VHDL y detallar minuciosamente paso a paso, tomar captures y realizar documento de word detallando cada paso la oferta es de 90 usdt. Se cuenta con la tarjeta en físico por lo cual se ofrece conexión remota

    Arduino Electronics Microcontroller Verilog / VHDL
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    VHDL test procedure and test bench implementation Ended

    VHDL test procedure and test bench implementation

    Electrical Engineering Engineering FPGA Matlab and Mathematica Verilog / VHDL
    $306 (Avg Bid)
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    VHDL designer -- 2 Ended

    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $351 (Avg Bid)
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    VHDL designer Ended

    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $347 (Avg Bid)
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    Need to convert MATLAB code to synthesizable VHDL code Ended

    Need to convert MATLAB code to synthesizable VHDL code. I am using DE2 FPGA board for testing

    Electrical Engineering FPGA LabVIEW Matlab and Mathematica Verilog / VHDL
    $80 (Avg Bid)
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    8 bit counter and BCD counter Ended

    -Write a VHDL file for an 8-bit counter with active-LOW asynchronous clear, active-HIGH synchronous load, active-HIGH count enable, and a directional input that makes the circuit count up when DIRECTION = 1 and down when DIRECTION = 0. - Write a set of simulation criteria that verifies the operation of the counter. The simulation must contain one complete cycle of the counter and test all functions. It must show that the synchronous load really is synchronous and that the clear has precedence over load, which in turn has precedence over count enable. -Write a VHDL file for a two-digit BCD counter with active-LOW asynchronous clear, active- HIGH synchronous load, and an active-HIGH count enable. -The counter must count up from 00 to 09, then 10 to 19, and so on until it reache...

    Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL
    $27 (Avg Bid)
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    Convert MATLAB code to VHDL code Ended

    Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.

    Electrical Engineering FPGA LabVIEW Matlab and Mathematica Verilog / VHDL
    $75 (Avg Bid)
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